Chapter 4: Development Board Setup
Factory Default Switch Settings
2. Set DIP switch bank (SW4) to match Table 4–2 and Figure 4–1 .
Table 4–2. SW4 Dip Switch Settings
4–3
Switch
Board
Label
Function
Default
Position
Switch 1 has the following options:
1
DIP0
When on, reserved.
Off
When off, reserved.
Switch 2 has the following options:
2
DIP1
When on, reserved.
Off
When off, reserved.
Switch 3 has the following options:
3
DIP2
When on, reserved.
Off
When off, reserved.
Switch 4 has the following options:
4
USR LOAD
When on, the PFL loads the user hardware 1 design on power up.
Off
When off, the PFL loads the factory design on power up.
Switch 5 has the following options:
5
PWR MON
When on, reserved.
Off
When off, reserved.
Switch 6 has the following options:
6
USB DISn
When on, reserved.
Off
When off, reserved.
Switch 7 has the following options:
7
CLK EN
When on, all on-board oscillators are enabled.
On
When off, on-board oscillators to the FPGA are disabled.
Switch 8 has the following options:
8
CLK SEL
When on, programmable oscillator clock (U30) is selected.
On
When off, LVPECL SMA clock (J10 and J11) is selected.
3. Set the board jumpers to match Table 4–3 and Figure 4–1 .
Table 4–3. JTAG Chain Jumper Settings (Part 1 of 2)
Board
Reference
Board
Label
Function
Default
Shunt Position
This jumper has the following options:
Installing the shunt removes the MAX II EPM2210 device from the
J9 pins 1-2
MAX DIS
JTAG chain.
Removing the shunt includes the MAX II EPM2210 device in the
Not installed
JTAG chain.
This jumper has the following options:
J9 pins 3-4
HSMA DIS
Installing the shunt removes HSMC port A from the JTAG chain.
Installed
July 2010 Altera Corporation
Removing the shunt includes HSMC port A in the JTAG chain.
Arria II GX FPGA Development Kit, 6G Edition User Guide
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